3-D Transient Analysis of TSV-Induced Substrate Noise: Improved Noise Reduction in 3-D-ICs With Incorporation of Guarding Structures
نویسندگان
چکیده
منابع مشابه
Power Grid Noise in TSV-Based 3-D Integrated Systems
A 3-D test circuit examining power grid noise in a 3-D integrated stack has been designed, fabricated, and tested. Fabrication and vertical bonding were performed by MIT Lincoln Laboratory for a 150 nm, three metal layer SOI process. Three wafers are vertically bonded to form a 3-D stack. Noise analysis of a power delivery topology is described. The effect of the through silicon via (TSV) densi...
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ژورنال
عنوان ژورنال: IEEE Electron Device Letters
سال: 2014
ISSN: 0741-3106,1558-0563
DOI: 10.1109/led.2014.2318301